This invention relates to the fabrication of semiconductor devices as it applies to thick films, and more specifically, to high aspect ratio photolithographic processes.
The use of high energy ion implantation has found a growing number of uses in the fabrication of semiconductor devices, such as retrograde well CMOS, advanced processes used in well engineering, or other high energy implant uses. As the energies used increase through several hundred KeV into the MeV range, ever thicker photoresists are needed to shield those areas to be protected from the implantation. At the same time, the feature size of such devices has become smaller. These competing aims of decreasing scale, down to 0.35 xcexcm and smaller CMOS processes, and increasing energy, into the MeV range, requires narrower areas of thicker resists, leading to higher aspect ratios, defined here as the thickness of the photoresist to width of the mask line. Producing a photoresist process capable of meeting these conflicting demands is of great importance as process techniques advance.
FIG. 1 is a flowchart of a conventional single-layer photolithographic process used in a typical lower energy ion implantation. First, in step 10 a photosensitive layer of a novolak positive photoresist is formed on the upper most surface of a silicon substrate previously subjected to a hexamethyldisanzane (HMDS) treatment to improve adhesion. The film thickness is typically less than 2.0 microns. This film is then prebaked, or softbaked, in step 20, customarily at 80-105xc2x0 C., with a value of 90xc2x0 C. typically, for anywhere between 30 and 60 seconds. The purpose of the prebake is to drive off the casting solvent in the photoresist. A pattern in the resist film is formed in step 30 utilizing ultraviolet light that is selectively irradiated onto the resist layer using a reticle. In step 40 the film is post exposure baked (PEB) at the higher temperature of 110-120xc2x0 C., with a value of 115xc2x0 C. typical, for 30-60 seconds. This post expose bake significantly reduces the standing wave effect in the film from the exposure.
The exposed film is then developed in an aqueous developer, step 50. Spray, single or double puddle, or hybrid xe2x80x9cspuddlexe2x80x9d development processes lasting 60 to 90 seconds are common. In the case of a positive resist, the developer removes that portion that has been exposed by the ultraviolet light.
Typically, the now patterned resist film is ultraviolet stabilized after being baked again at 110-120xc2x0 C. for 30-60 seconds to drive off remaining solvents and chemically crosslink the film in steps 60 and 70. Not all processes include the deep UV stabilization step and the hardbake of step 60 additionally helps to dry the wafer from step 50 when step 70 is absent. A standard stabilization in a deep UV tool will heat and expose the resist at the same time, typically heating from a temperature of 110xc2x0 C. to 220xc2x0 C. with the lamp on during portions of the process. During the stabilization process, the UV and thermal energies work together to remove residual solvents, moisture, and by-products (primarily nitrogen) from the photoactive compound decomposition and to chemically cross link the resist. Once the stabilization is complete, the resist is now ready for the ion implantation of step 80.
In this conventional process, a pattern is transferred from the reticle into the resist film. The pattern transfer process is limited. The linewidth of the formed pattern is required to have the same linewidth as the pattern on the reticle. For common thicknesses less than 1.5 xcexcm, this is well know in the art. As the resist thickness increases and/or as the aspect ratios increase, the patterning process becomes extremely difficult. With the application of high energy ion implantation, such as for CMOS or other advanced well processing, thicker photoresist films with high aspect ratios are required, where a high aspect ratio is defined as greater than 2:1.
In one example of a high energy implantation, a retrograde twin well CMOS process forms two types of well structures in the same device. There are n-well and p-well regions in contact with the substrate. These twin well structures are formed by utilizing a high energy (MeV) ion implantation to place the dopant beneath a thin oxide layer and into the underlying silicon. A photoresist film consistent with high energy implantation is required to successfully block the implant species from being implanted in unwanted device regions. These resists may need to be 3-4 xcexcm or thicker. Combined with the decreasing scale used of critical dimensions, some recent CMOS device design rules require ratios of 4:1 or greater. These challenges tax the capability of any photolithographic process.
A conventional single-layer photoresist process utilized in a high energy ion implantation application produces some very adverse effects. In thicker films, if residual casting solvents are allowed to remain in the resist film, a detrimental sidewall differential and other pattern deformations could occur which dramatically distort the printed image. These phenomena effect both isolated and dense features, but are particularly acute in isolated features. Maintaining acceptable critical dimension stability and uniformity, step coverage, and process latitudes all become increasingly difficult as the aspect ratio increases. Appropriate process conditions are needed to both minimize outgassing at implantation and produce a resist of uniformly hardened through its cross-section.
Proper choices for the parameters of the various bake stages are needed to minimize these problems. Due to the chemical properties of the both the resist and the solvent, the glass transition and decomposition temperatures of the resist along with the volatility and boiling point of the casting solvent must all be considered. Although using higher bake temperatures may cause the solvent to evaporate and defuse more readily, above a certain temperature the resist components will begin to deteriorate. Therefore a difficult balance must be maintained. For the thicker resist layer needed for higher energy implantation, these difficulties become much greater. If the solvent is too volatile, or a bake temperature to high, the solvent may be driven from the outer portions of the resist too rapidly, thereby forming a skin which will seal in the solvents inside the resist film. This last problem can lead to unacceptable resist loss as the ions can wear through the hard outer layer into a soft center that is quickly lost. Also, when bombarded with such high energy ions, an improperly formed resist of the required aspect ratio may collapse. Additionally, this produces a degradation of the other required properties of the resist mentioned above which the art has learned to overcome for thinner resists, such as stability and uniformity for critical dimensions, step coverage, and process latitudes.
There are many other uses for high aspect photoresist in addition to their use in high energy implantation. The following methods have been known as methods of forming thick film photoresists patterns with high aspect ratios:
(A) In U.S. Pat. No. 5,262,281 a method is disclosed in the patterning of thick resists utilized in device and mask manufacture that provides excellent resolution and sensitivity, but this is obtained using a specific composition. Specifically, the composition involves polymers having recurring pendant acid labile a-alkoxyalkyl carboxylic acid ester and/or hydroxyaromatic ether moieties in the presence of a substance that is an acid generator upon exposure to actinic radiation.
(B) In U.S. Pat. No. 5,330,881 discloses a resist patterning process which allows generation of very thick ( greater than 3.0 xcexcm), vertically-walled resist patterns which allow for the subsequent deposition or etching operations. The application for this process is for magnetic thin film heads and other devices requiring high aspect ratios. The invention utilizes a barrier layer in conjunction with a contrast enhancement layer to provide the vertically-walled resist patterns.
(C) In U.S. Pat. No. 5,340,702, a method is disclosed for accurately forming a thick, fine pattern of photoresist. This is accomplished by (1) forming a film of a positive photoresist on a substrate, having a thickness of 50 to 500 microns, (2) forming a light-shielding film (consisting of lead, tin, indium, copper and alloys of these) directly on a surface of the film of photoresist, (3) processing the light-shielding film into the pattern, (4) exposing the film of the positive photo resist and (5) developing the exposed film of photoresist. The application for this process is in the production of a printed circuit substrate. The method is used to accurately pattern resists having a thickness of 50 to 500 microns.
(D) Work has been done on very thick photoresists for micro-device work, such as U.S. Pat. Nos. 5,356,828 and 5,722,162. Although much of this work involves thick or extremely thick photoresists, it is done at a much larger scale, well above the feature size needed here.
(E) Other work, such as for example Chen et al., xe2x80x9cProcess Development for 180-mm Structures Using Interferometric Lithography and I-Line Photoresistxe2x80x9d, describes photoresists with a high aspect ratio, but done with thinner resists. It does not describe photoresists of the thickness needed here and works at a more common resist thickness in the range of 1 xcexcm. Even for such thinner photoresists, this paper describes many of the problems encountered for high aspect ratios.
None of this work describes a method to produce a photoresist suitable for high energy ion implantation with both energies increasing into the MeV range and scale decreasing down to a 0.35 xcexcm CMOS process. This requires a highly stable photolithographic process which can produce a resist with aspect ratios of 4:1 or even higher.
Therefore, it is the primary object of the present invention to present a method of producing a photoresist for high energy ion implantation for mask level pitches of 2.0 xcexcm or less and post softbake aspect ratios of over 3:1.
Consequently, it is another object to present a method of producing a photoresist thicknesses of more than 3 to 4 microns and widths which may be 1 micron or less, resulting in aspect ratios of 3:1 to 4:1 or greater. The photolithographic method should improve critical dimension stability and uniformity, step coverage, and process latitudes. The method should also be processed to minimize unexposed resist loss and isolated/dense linewidth biases, along with the properties of decreasing nitrogen outgassing and increasing contrast through develop.
It is a further object to use such photoresists to form a retrograde twin well, 0.35 xcexcm CMOS semiconductor device.
These and additional objects are accomplished by the various aspects of the present invention, wherein, briefly and generally, according to one such aspect, a highly stable photolithographic process is defined. In a preferred embodiment, the photoresist film is applied using a commercial coating system at some final speed to achieve the required film thickness of up to 4.2 xcexcm using a commercial, high contrast, I-line novolak photoresist. The photoresist film is then prebaked (softbaked) at 115 to 120xc2x0 C. for 90 to 240 seconds to remove the casting solvent from the film. To define the latent image, a commercial step and repeat I-line system is utilized. After exposure, the film is then post exposure baked at 115 to 120xc2x0 C. for 90 to 240 seconds to remove additional casting solvent and wafer and to reduce the standing waves from exposure. The film is then developed using a 0.26N, metal-ion-free developer containing 2.3% TMAH by weight in water. In one variation, a commercial deep UV system is used to then stabilize the film by ramping from an initial idle temperature of 90 to 115xc2x0 C. to a final temperature of 220 to 230xc2x0 C. while incorporating the use of an UV lamp. Another variation utilizes a non-thermal electron beam stabilization. This process is highly stable and results in extremely non-typical post softbake aspect ratios of up to 4.2:1.
According to other aspects of the present invention, this process uses non-typical softbake conditions. It was determined that for softbake conditions at lower temperature and time, residual solvents are retained in the photoresist film producing a detrimental sidewall differential. This phenomenon was worse in isolated features, but effected both isolated and dense features. The higher softbake conditions remove the majority of the residual solvent and eliminate the sidewall differential.
A further aspect is that the photoresists allow the use of implantation of ions with energies into the MeV range for mask level pitches of 2.0 xcexcm and smaller. This is done by use of a photoresist of sufficient thickness and sufficient narrowness produced by the described method.
An additional aspect is the use of such photoresists and high energy ion implantation for a retrograde twin well, 0.35 xcexcm CMOS process. The p-well and n-well layers are implanted utilizing MeV boron and phosphorous respectively.
All these aspects have applications to the high aspect ratio, photolithographic method for high energy ion implantation according to the present invention. Additional objects, advantages, and features of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.